1. Field of the Invention
This invention generally relates to semiconductor integrated device design and fabrication and, more particularly, to processes for isolating devices using trench isolation techniques.
2. Description of the Related Art
As semiconductor integrated circuit technology advances to Ultra Large Scale Integration (ULSI) technologies, the devices on the wafers shrink to sub-micron dimensions and the circuit density increases to several million devices per chip. As such, the manufacturability and reliability of these sub-micron dimensioned devices are of great importance to the semiconductor industry and have received increasing attention recently.
For a given chip size, an increase in the number of active circuit components, i.e., active devices, typically requires that the devices be placed in close proximity to each other, thus forcing a corresponding reduction in the surface area of the circuit that can be occupied by electrical isolation structures. It is understood that active devices on a chip surface often have to be electrically isolated from adjacent devices to prevent adjacent devices from altering the operation of other adjacent devices. The trend for reducing the chip surface area consumed by electrical isolation structures, while maintaining the necessary electrical isolation of adjacent active components, has led to the development of several different techniques for isolating devices in a manner that reduces the surface space occupied by isolation structures.
The most common isolation fabrication technique is a process known as LOCOS (for LOCalized Oxidation of Silicon). In the LOCOS process, regions of the substrate are oxidized to form isolation structures known as field oxide regions, which separate adjacent active areas that will contain active devices. In the conventional LOCOS technique, the process typically begins with the growth of a thin pad oxide layer over the wafer surface. In general, this pad oxide layer is a layer of SiO2 (silicon dioxide) and is relatively thin. Following this, a thicker layer of silicon nitride mask is deposited on top of the pad oxide layer and lithographically defined to retain the nitride over the active device regions of the wafer. The nitride layer is etched from the area between the active device areas where the field oxide (silicon dioxide) is then thermally grown.
Although the LOCOS process offers high reliability and proven high volume manufacturing compatibility, this technique has some well-known disadvantages. The first disadvantage of the process is the problem of active area loss due to lateral encroachment of the growing field oxide. In semiconductor technology, this problem is known as “bird's beak” encroachment and it is the result of lateral diffusion of the oxidants at the edges of the nitride masking stack. The bird's beak encroachment causes the oxide layer to grow under the nitride masking stack and limits the usable active device areas. Thus, a large area on the chip is lost after the field oxidation is complete.
Another limitation of LOCOS isolation technologies for sub-micron structures is a phenomenon often referred to as “Kooi” effect or “white ribbon” effect. The Kooi effect occurs during the field oxide growth step where a thin silicon nitride layer can also form on the silicon surface at the pad oxide/silicon interface as a result of the reaction of ammonia (NH3) and silicon. The ammonia is generated from the reaction between water vapor and the masking nitride during the field oxidation step. Subsequently, when the gate oxide is grown, the growth rate becomes impeded at the locations where the silicon nitride has formed. The gate oxide is thus thinner at these locations than elsewhere, causing low-voltage breakdown of the gate oxide. One common way to eliminate this problem is to grow a sacrificial oxide layer after the masking stack etch. The sacrificial oxide is then removed before growing the final gate oxide. However, the additional process steps involved for eliminating the Kooi effect add to the cost and complexity of ULSI fabrication.
Such disadvantages of the conventional LOCOS process motivated the development of alternative isolation approaches. Among a few other isolation technologies, which have focussed their efforts on eliminating the bird's beak and the Kooi effects, the “trench isolation” technique can be considered as an alternative isolation technology to the LOCOS process. In this technique, the field oxide regions are basically formed by etching trenches into the silicon substrate, so as to define the field oxide regions, and subsequently filling the trenches with a CVD (chemical vapor deposited) oxide, such as SiO2.
An exemplary trench isolation technique initially begins with depositing a suitable masking material on top of a substrate. A typical masking material may comprise a photoresist, silicon nitride, silicon dioxide or combinations thereof. The masking stack is then etched to define the locations on the substrate where the trenches are to be formed. Subsequently, trenches of varying widths and depths are anisotropically etched into the silicon substrate through the patterned masking layer. A CVD oxide, preferably a layer of SiO2, is then deposited over the wafer, which completely fills the trenches and covers the top of the masking stack. The CVD oxide deposition is followed by an etchback process to etch the masking stack and the excessive CVD-oxide from the surface of the substrate. During the etchback process, the masking stack and the CVD-oxide are dry etched at the same rate to retain the CVD-oxide only in the trenches and to level its top surface with the original surface of the silicon substrate. Consequently, the field isolation regions produced by the trench isolation technique provide a significantly planar isolation layer while eliminating the bird's beak and the Kooi effect.
However, as device dimensions become smaller and trench widths become narrower, the trenches refilled by current CVD techniques fail to provide defect free field oxide isolation layers. As described above, the CVD-oxide refill process proceeds by means of a conformal oxide covering of both the trench surfaces and the top of the masking layers. In the trenches, the conformal layers of oxide are initially formed on the side walls and they are grown in size outward into the center of the trench to where the oxide layers meet.
Unfortunately, as the surfaces of the two oxide layers formed on the opposite side walls meet in the center of the trench to close and fill the trench, voids or a seam line can begin to form between the two meeting surfaces. These voids and seam lines are defective formations which can greatly affect the stress distribution in the oxide filling the trenches and create localized stress points which can be etched faster than the rest of the oxide filling the trenches during subsequent etch steps of the wafer.
As a result, divots or a non-planar surface may form during the subsequent processing steps thereby impairing the isolation capability of the isolation layer. Moreover, if the trenches of widely varying widths are filled, the narrow trenches must be over-filled in order for the wider trenches to be filled completely. Thus, the thickness of the top-surface-deposited film will vary making planarization very difficult. This problem is particularly difficult in ULSI applications where the isolation regions are so small. Hence, there is a need in current semiconductor technology for improved techniques to eliminate the problems occurring during trench isolation processes. To this end, there is a need for improved trench isolation techniques which provide a more defect free isolation structure and more planar field oxide regions.